Tech in Electronics Engineering/Electrical Engineering, VLSI  Prior Industry experience in Design Verification at SoC level, with hands on and solid depth on DV  Strong Digital logic, Circuit theory fundamentals  Should have independently handled design verification activities at SoC level.  Should have good understanding of Device architecture, functional aspects to map to DV scenarios  Skills should include: Verilog/VHDL, Perl, TCL, and shell scripts, C, automation expertise  Expertise in using simulation tools (ncsim, VCS,modelsim)  Good communication and presentation skills and team work.

Additional Preferred Qualifications:  Exposure to any other HVLs (specman, system verilog, SVA) as a developer / user  Hands on experience on gate level simulations  Post silicon debug experiences on tester  In depth understanding of modules functionality(eg., Ethernet, USBs, power management schemes)  Exposure to any of emulation/prototyping platforms (palladium, FPGA)  ARM family architecture understanding and the hands on experience Primary Responsibilities:  Own IP integration verification at SoC for multiple modules (From Verification plan creation to coverage/quality closure)  Develop Verification plan, test plans, tests and simulations at all phases (RTL, GLS), tracking of the activities  Good interaction with integration team, specification team, and rest of DV members Secondary Responsibilities include one or more of below:  Own the flows to enable automation  Gate level debugs, test vector creation for silicon bringups Complex Tasks:  SoC designs in typically have very tight performance, power, and area targets set by the high-volume high-performance markets, and high configurability for catering to the needs of a wide-variety of target applications.

 Meeting such conflicting requirements often demands extensive planning and pure innovation along with robust functional verification to ensure products ramp faster.  Chips that are being developed in India DSP team integrate high performance and power optimized processor cores along with analog and digital IPs that are implemented across sites world-wide.

 Candidate Should be able to understand system-level details, have excellent problem solving skills to resolve complex issues as they occur.  The SoC Verification responsibilities involve understanding the architecture thoroughly to bring out any architectural issues, and also ensuring the quality/robustness of the device with high quality verification, and attaining the DV metric goals.

 The candidate also needs to work with application teams to debug, trouble shoot any of the failures on prototyping environments pre and post silicon (less)